Aefinity AI

L02 Positive Q2 · Graphics cards and shortcuts

An NVIDIA GPU reproduces the CPU reference digest (Tesla P100)

QuestionDoes the same AI output come out bit for bit on a graphics card, not just on other CPUs?

Run by us; no unaffiliated reproduction

01Why it matters

Most AI runs on graphics cards. A reproducibility claim that only holds on CPUs would not cover where the work is done.

02Method, step by step

  1. Write an independent CUDA implementation of the same spec.
  2. Run the four test vectors on a Kaggle Tesla P100 with the internet disabled.
  3. Compare the GPU digests with the CPU digests.
  4. Check, by sampling GPU occupancy and inspecting the compiled code, that the work really ran on the GPU.

Method as recorded

An independent CUDA implementation of spec v0.3b on a Kaggle Tesla P100 (sm_60, CUDA 12.8, internet disabled), SmolLM2-135M, four vectors (16 and 128 tokens, sequential and a candidate tree order). Run by us. The CUDA source and run recipe are not published.

03Results, exact and sourced

  1. R1All four vectors matched the CPU digests on the GPU. Only the 16-token sequential vector is the normative v0.3b vector; the other three are informative, and the two tree-order vectors belong to a v0.4 candidate that is not normative.

    **Status: PASS. Run of 2026-09-08 12:07 UTC, NVIDIA Tesla P100-PCIE-16GB (sm_60, Pascal), CUDA 12.8.**

    Verbatim source cis2-spec / GPU_RESULT.md

  2. R2Two earlier GPU runs were false positives (the binary was really built for the CPU) and are withdrawn.

    Earlier attempts v6 and v7 were false positives and are withdrawn

    Verbatim source cis2-spec / GPU_RESULT.md

04What it does NOT show

Anything about speed, newer GPU generations, tensor cores, batching or multiple GPUs; and the CUDA source is not public, so outsiders cannot rerun our port.

05Scope and caveats

  • One GPU generation (Pascal), one driver and compiler, one model (SmolLM2-135M), one prompt, horizon up to 128 tokens.
  • Correctness only: no performance or timing claim; no tensor-core, batched, multi-stream or multi-GPU paths; nothing about Ampere, Hopper or Blackwell.
  • The CUDA port is not published, so outsiders cannot rerun it from the repo. The source says anyone can write their own CUDA implementation from the spec and compare against the published digest.
  • Do not cite the withdrawn v6 or v7 runs; the claim rests only on the corrected v8 run. An earlier v5 run (2026-09-06) matched the same digests but did not establish device execution, and v8 closed that gap.
  • Only the 16-token sequential vector is normative; the other three are informative and the tree order is a v0.4 candidate, not part of v0.3b.
  • Device execution evidence is occupancy sampling (nvidia-smi, 10 and 11 samples) plus SASS inspection, not a performance measurement.
  • Run by us; no unaffiliated reproduction.

06Outcome

Positive

The check worked as expected, within the stated scope.

07What we learned

Our own early GPU runs passed for the wrong reason. A re-run caught it, and the claim now rests only on the corrected run.

08Check it yourself

Read the result page (links above). Our CUDA source is not published. The source says anyone can write their own CUDA implementation from the public spec and compare it against the published digest.

  • L03
    Positive

    Batching and precision on a Tesla T4: which shortcuts change the digest

    In our fp32 test, the pinned order of operations decided the digest. The same order matched on CPU and GPU, and a different order broke it, which is what a digest is supposed to detect. This is one matmul on one GPU type, so it shows the check works there, not that it holds everywhere.

    Q2

  • L01
    Positive

    CIS-2: the same AI output, bit for bit, on different machines

    With the arithmetic pinned in writing, one fp32 digest reproduced across AVX2 and scalar x86, an aarch64 phone and an AVX-512 cloud CPU, in our own runs. Until an outsider runs it, the claim stays 'reproduced by us'.

    Q1